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functional block diagram output side control circuit input side control circuit emi filter output filter +v out return + sense adjust status v aux inhibit sync i share temp ? in +v in fixed frequency dual interleaved power train ?sense return return +v out +v out rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a addc02808pb features 28 v dc input, 8 v dc @ 25 a, 200 w pulse output integral emi filter ultrafast transient response minimal output voltage deviation low weight: 80 grams navmat derated many protection and system features applications distrib uted power architecture for driving t/r modules motor and actuator drivers general description the addc02808pb hybrid military dc/dc converter is com- pensated specifically for pulse applications where fast transient response and minimum output voltage deviation are required. it is also designed to deliver very high, pulsed output power. the unit is designed for high reliability and high performance applications where saving space and/or weight are critical. the addc02808pb has been characterized over a wide variety of load conditions. its transient response has been set to insure output stability over a broad range of load capacitance. for applications that require factory modified compensation optimized for a specific load, or for applications that require a different output voltage than 8 v dc, contact the factory. the addc02808pb is available in a hermetically sealed, molybdenum based hybrid package and is easily heatsink mountable. for mil-std-883 devices, contact the factory for availability. 28 v, 200 w pulsed dc/dc converter with integral emi filter product highlights 1. 120 w/cubic inch pulsed power density with an integral emi filter 2. ultrafast transient response time with minimum output voltage deviation 3. light weight: 80 grams 4. operational and survivable over a wide range of input conditions: 16 vC50 v dc; survives low line, high line 5. high reliability; navmat derated 6. protection features include: output overvoltage protection output short circuit current protection thermal monitor/shutdown input overvoltage shutdown input transient protection 7. system level features include: current sharing for parallel operation logic level disable output status signal synchronization for multiple units input referenced auxiliary voltage supply one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 obsolete
addc02808pbCspecifications electrical characteristics case test addc02808pb parameter temp level conditions min typ max units input characteristics steady state operating input voltage range 1 full vi i o = 1.25 a to 25 a pulsed 18 28 40 v abnormal operating input voltage range (per mil-std-704d) 1 full vi i o = 1.25 a to 25 a pulsed 16 50 v input overvoltage shutdown +25 c i 50 52.5 55 v no load input current +25 c vi 45 100 ma disabled input current +25 cvi 1 5 ma output characteristics 2, 3 output voltage (v o ) +25 ci i o = 1.25 a to 25 a, v in = 18 v to 40 v dc 7.92 8.00 8.08 v full vi i o = 1.25 a to 25 a, v in = 18 v to 40 v dc 7.84 8.16 v full vi i o = 1.25 a to 20 a, v in = 16 v to 50 v dc 7.84 8.16 v line regulation +25 cvi i o = 25 a pulsed, v in = 18 v to 40 v dc 1 5 mv load regulation +25 cvi v in = 28 v dc, i o = 1.25 a to 25 a pulsed 2.5 10 mv output ripple/noise 4 +25 ci i o = 25 a, 5 khz C 2 mhz bw 40 60 mv p-p output current (i o ) 5 full vi v in = 18 v to 40 v dc, pulsed 1.25 25 a output overvoltage protection +25 cv i o = 25 a, open remote sense connection 120 % v o nom output current limit +25 cv v o = 90% v out nom 130 % i o max output short circuit current +25 c i 45 m w r short circuit 60 m w 40 a isolation characteristics isolation resistance +25 c i input to output or any pin to case at 500 v dc 100 m w dynamic characteristics 4 step changes in load (min to max) +25 c i (reference section entitled transient response) step changes in load (max to min) (reference section entitled response at end of pulse) soft start turn-on time +25 ci i o = 25 a, from inhibit high to status high 6 10 ms thermal characteristics efficiency +25 ci i o = 12.5 a 79 80 % full vi i o = 12.5 a 78 % +25 ci i o = 25 a 75 76 % full vi i o = 25 a 72.5 % hottest junction temperature 5 +90 cv i o = 25 a 110 c control characteristics clock frequency full vi i o = 2 a 0.85 0.99 mhz adjust (pin 3) v adj +25 c i 3.1 3.2 3.3 v status (pin 4) v oh +25 ci i oh = 400 m a 2.4 4.0 v v ol +25 ci i ol = 1 ma 0.15 0.7 v v aux (pin 5) v o (nom) +25 ci i aux = 5 ma, load current = 12.5 a 14.9 15.15 15.4 v inhibit (pin 6) v il +25 ci 0.5 v i il +25 ci v il = 0.5 v 1.2 ma v i (open circuit) +25 ci 15 v sync (pin 7) 6 v ih +25 c i 4.0 v i ih +25 ci v ih = 7.0 v 150 m a i share (pin 8) +25 ci i o = 20 a 2.45 2.55 2.65 v temp (pin 9) +25 c v 3.90 v notes 1 50 v dc upper limit rated for transient condition of up to 50 ms. 16 v dc lower limit rated for continuous operation during emergency condition. steady state and abnormal input voltage range require source impedance sufficient to insure input stability at low line. see sections entitled system instability considerations and input voltage range. 2 measured at the remote sense points. 3 unit regulates output voltage to zero load; tests performed at low continuous load and 200 w pulsed load. 4 c load = 1,000 m f. output ripple/noise measured at converter output; may be smaller at external load capacitance. unit is stable for c load ranging from 500 m f to 4,000 m f. 5 refer to section entitled pulse output power vs. pulse length for more information. 6 unit has internal pull-down; refer to section entitled pin 7 (sync). specifications subject to change without notice. rev. 0 C2C (t c = +25 8 c, v in = 28 v dc 6 0.5 v dc, unless otherwise noted; full temperature range is C55 8 c to +90 8 c; all temperatures are case and t c is the temperature measured at the center of the package bottom.) obsolete
addc02808pb rev. 0 C3C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . 50 v dc, C0.5 v dc sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0 v dc, C0.5 v dc i share . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v dc, C0.5 v dc temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v dc, C0.3 v dc common-mode voltage, input to output . . . . . . . . . 500 v dc lead soldering temp (10 sec) . . . . . . . . . . . . . . . . . . . +300 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . . +150 c maximum case operating temperature . . . . . . . . . . . +125 c *absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. ordering guide operating temperature device range (case) description addc02808pbkv C40 c to +85 c hermetic package addc02808pbtv C55 c to +90 c hermetic package addc02808pbtv/883b* C55 c to +125 c hermetic package *contact factory. explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c, and sample tested at specified temperatures. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C all devices are 100% production tested at +25 c. 100% production tested at temperature extremes for military temperature devices; guaranteed by design and characterization testing for industrial devices. pin descriptions pin no. name function 1 Csense feedback loop connection for remote sensing output voltage. must always be connected to output return for proper operation. 2 +sense feedback loop connection for remote sensing output voltage. must always be connected to +v out for proper operation. 3 adjust adjusts output voltage setpoint. 4 status indicates output voltage is within 5% of nominal. active high referenced to Csense (pin 1). 5v aux low level dc auxiliary voltage supply refer- enced to input return (pin 10). 6 inhibit power supply inhibit. active low and refer- enced to input return (pin 10). 7 sync clock synchronization input for multiple units; referenced to input return (pin 10). 8i share current share pin which allows paralleled units to share current typically within 5% at full load; referenced to input return (pin 10). 9 temp case temperature indicator and temperature shutdown override; referenced to input return (pin 10). 10 Cv in input return. 11 +v in +28 v nominal input bus. 12 +v out +8 v dc output. 13 +v out +8 v dc output. 14 +v out +8 v dc output. 15 return output return. 16 return output return. 17 return output return. pin configuration 1 11 12 17 top view warning! esd sensitive device obsolete
addc02808pbCtypical performance curves rev. 0 C4C output power ?watts 82 68 020 percentage 40 60 80 100 80 78 76 120 140 160 180 200 74 72 70 40v 28v 18v figure 1. efficiency vs. line and load at +25 c (load pulse width of 50 ms) t case 79 79 76 ?5 95 ?5 efficiency ?percentage ?5 ?5 ?5 ? 78 78 77 77 5 1525354555657585 28v in , 150w peak figure 2. efficiency vs. case temperature ( c) (at nominal v in , 75% max load, load pulse width of 50 ms) peak output power ?watts 16.0 15.5 13.0 140 200 150 input voltage 160 170 180 190 15.0 14.5 13.5 14.0 figure 3. low line dropout vs. load at 90 c case temperature (load pulse width of 50 ms) t case 1.0 ?.0 ?5 95 ?5 ?5 ?5 ?5 ? 0.5 0.0 ?.5 5 1525354555657585 28v in , 150w peak v out deviation ?% figure 4. output voltage vs. case temperature ( c) 2v 10v 10 0% 100 90 1ms v o v inhibit figure 5. output voltage transient during turn-on with 0.1 a load displaying soft start when supply is enabled 100mv 10 0% 100 90 100? v o figure 6. output voltage transient response to a 1 a to 25 a step change in load, di/dt = 12 a/ m s, with 1,000 m f load capacitance (r esr = 10 m w ) obsolete
addc02808pb rev. 0 C5C frequency ?hz 0 ?0 ?00 10 50k 100 |as| ?db 1k 10k ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 figure 7. audio susceptibility (magnitude of v out /v in ) frequency ?hz 1k 0.1 10 100k 100 |z in | ? w 1k 10k 100 10 1 figure 8. incremental input impedance (magnitude) frequency ?hz 1 10 100k 100 |z out | ? w 1k 10k 0.1 0.01 0.001 figure 9. incremental output impedance (magnitude) 5mv 1mv 50? 020 volts 10 .5mv 100? frequency ?mhz figure 10. output frequency spectrum obsolete
addc02808pbCt ypical emi curves & test setup for 28 v in , 5 v dc out, 100 w converter rev. 0 C6C frequency ?mhz 130 0.01 0.0001 0.001 70 90 30 emission level ?db ? 110 50 conducted emissions ce?01 ce101? 4.5 amps figure 11. conducted emissions, mil-std-461d, ce101, +28 v hot line 100 w load frequency ?mhz 130 10 0.01 0.1 70 90 30 emission level ?db ? 110 50 1 conducted emissions ce?02 limit 28vdc figure 12. conducted emissions, mil-std-461d, ce102, +28 v hot line 100 w load frequency ?mhz 166 0.1 0.0001 0.001 106 126 66 emission level ?db/pt 146 86 0.01 re101 mil-std-461d re101? figure 13. radiated emissions, mil-std-461d, re101, 100 w load frequency ?mhz 90 10 0.01 0.1 30 50 ?0 emission level ?db ?/m 70 10 1 100 1000 radiated emissions re?02 re102? figure 14. radiated emissions, mil-std-461d, re102, vertical polarity, 100 w load +v in ? in +v out return case lisn 1/4 w 0.1? ground plane 82nf 82nf 2? 1 w 100? two meters of twisted cable note: 100? capacitor and 1 w resistor provide stabilization for 100? differential source inductance introduced by the lisns. refer to section on emi considerations for more information. lisn figure 15. s chematic of test setup for emi measurements obsolete
addc02808pb rev. 0 C7C basic operation the addc02808pb converter uses a flyback topology with dual interleaved power trains operating 180 out of phase. each power train switches at a fixed frequency of 500 khz, resulting in a 1 mhz fixed switching frequency as seen at the input and output of the converter. in a flyback topology, energy is stored in the inductor during one half portion of the switching cycle and is then transferred to the output filter during the next half portion. with two interleaved power trains, energy is transferred to the output filter during both halves of the switching cycle, resulting in smaller filters to meet the required ripple. a five pole differential input emi filter, along with a common- mode emi capacitor and careful attention to layout parasitics, is designed to meet all applicable requirements in mil-std-461d when installed in a typical system setup. due to the higher output level in this product compared to the 100 w continuous output products, input stability is more of a concern. as a result, the two inductors in the internal input emi filter have smaller values of inductance to mitigate input stability concerns. the effectiveness of the internal input emi filter is, therefore, slightly diminished compared to these other products. a more detailed discussion of ce102 and other emi issues is included in the section entitled emi considerations. the maximum available peak power out is 200 w and is based on a combination of maximum junction temperatures, maximum pulse width, and maximum duty cycle. refer to section entitled, pulsed output power vs. pulse length, for peak power derating curves for varying conditions. the unit is compensated for ultrafast transient response with minimum output voltage deviation. the compensation has been optimized and output stability insured for an external load capacitance in the range of 500 m f, 20 m w esr to 4,000 m f, 2.5 m w esr. peak performance and output stability are depen- dent on minimizing parasitic inductance and resistance in the con- nection from the converter to the load. the converter uses current mode control and employs a high performance opto-isolator in its feedback path to maintain isolation between input and output. the control circuit is designed to give a nearly constant output current as the output voltage drops from v o nom to v sc during a short circuit condition. it does not let the current fold back below the maximum rated output current. the output overvoltage protection circuitry, which is independent from the normal feedback loop, protects the load against a break in the remote sense leads. remote sense connections, which can be made at the load, can adjust for voltage drops of as much as 0.25 v dc between the converter and the load, thereby maintaining an accurate voltage level at the load. an input overvoltage protection feature shuts down the con- verter when the input voltage exceeds (nominally) 52.5 v dc. an internal temperature sensor shuts down the unit and prevents it from becoming too hot if the heat removal system fails. the temperature sensed is the case temperature and is factory set to trip at a nominal case temperature of 110 c to 115 c. the shut down temperature setting can be raised externally or disabled by the user. each unit has an inhibit pin that can be used to turn off the converter. this feature can be used to sequence the turn-on of multiple converters and to reduce input power draw during extended time in a no load condition. a sync pin, referenced to the input return line (pin 10), is available to synchronize multiple units to one switching frequency. this feature is particularly useful in eliminating beat frequencies which may cause increased output ripple on paralleled units. a current share pin (i share ) is available which permits paralleled units to share current typically within 5% at full load. a low level dc auxiliary voltage supply referenced to the input return line is provided for miscellaneous system use. pulsed output power vs. pulse length the maximum specified pulsed output power in the standard configuration of the addc02808pb is 200 w. this limit is based on issues of working down to the minimum input voltage, of providing a reasonable short circuit current limit, and so on. however, this power level assumes that the junction temperatures of the converters power semiconductor devices have not exceeded 110 c. for short pulse lengths and low duty cycles, this condition will be met. otherwise, the pulsed output power will have to be reduced to keep the junction temperatures below 110 c if navmat guidelines are to be followed. figures 16 and 17 show the tradeoff that must be made between the highest allowable pulsed output power and the pulse length. notice that for each curve, as the pulse length is made longer, the pulsed power that causes a 110 c junction temperature to be reached is lower. the curves are provided for two baseplate temperatures (25 c and 90 c) and three average output powers. the duty cycle that corresponds to any point on a curve can be calculated by dividing the average power by the pulsed power for that point. the curves represent typical upper limits; operation anywhere below the curves is acceptable and will result in cooler junctions. the addc02808pb is designed to deliver a continuous 100 watts to its output while keeping its hottest junction tempera- ture below 110 c with a baseplate temperature of 90 c. pulse width ?ms peak power ?w 250 200 0 0 700 100 200 300 400 500 600 150 100 50 maximum peak power limit maximum continuous power limit 100w ave 50w ave 10w ave figure 16. largest on-state power vs. pulse width that maintains t jmax 110 c at 25 c baseplate obsolete
addc02808pb rev. 0 C8C pulse width ?ms peak power ?w 250 200 0 0 150 50 100 150 100 50 maximum peak power limit maximum continuous power limit 100w ave 50w ave 10w ave 25 75 125 figure 17. largest on-state power vs. pulse width that maintains t jmax 110 c at 90 c baseplate transient response the standard addc02808pb is designed to deliver large changes, or pulses, in load current with minimum output voltage deviation and an ultrafast return to the nominal output voltage. the compensation of the feedback loop is optimized, and output stability is insured, for a broad range of external load capacitance extending from 500 m f (r esr = 20 m w ) to 4,000 m f (r esr = 2.5 m w ). the variables that impact pulse performance (the maximum output voltage deviation and the settling time) are: 1. size of step change in the output current. 2. amount of external load capacitance. 3. internal compensation of the feedback loop (factory set). 4. connection from converter output to load. extensive modeling of the converter with adi proprietary software permits analysis and prediction of the impact each of these parameters has on the pulse response. the analyses in this data sheet are based on the load capacitance being comprised of 100 m f, 100 m w tantalum load capacitors such as the csr21 style. figure 18 is the prediction of the standard converters response to a 24 a step change in load current (from 1 a to 25 a) with a load capacitance of 1,000 m f (r esr = 10 m w ). this is very close to the measured pulse response under the same conditions shown in figure 6. 8.1 7.4 ?00 800 ?00 v o ?v 0 100 200 300 400 500 600 700 8 7.9 7.8 7.7 7.6 7.5 time ?? figure 18. predicted response to 24 a step change in load current, di/dt = 12 a/ m s, for c load = 1,000 m f and r esr = 10 m w 8.1 7.4 ?00 800 ?00 v o ?v 0 100 200 300 400 500 600 700 8 7.9 7.8 7.7 7.6 7.5 time ?? 12a step change 24a step change figure 19. predicted response to 12 a and 24 a step change in load current, di/dt = 12 a/ m s, for c load = 1000 m f and r esr = 10 m w step change if the step change is less than 24 a, the pulse response will im- prove. for instance, with a 12 a step change, figure 19 shows a comparison of the response for a 24 a step change and a 12 a step change in load. load capacitance varying the external load capacitance and associated r esr be- tween the range of c load = 500 m f (r esr = 20 m w ) and c load = 4,000 m f (r esr = 2.5 m w ) results in the predicted waveforms shown in figures 20, 21, and 22. as can be seen, the larger the capacitor, the smaller the deviation, but the longer the settling time. table i lists the maximum output voltage deviations and settling times for the four combinations of c load and r esr men- tioned above. note that these are based on the standard com- pensation for the feedback loop. table i. output response to a 24 a (1 aC25 a) step in load current (standard compensation) typical settling time see c load r esr deviation (within 1%) figure 500 m f 20 m w C7% 150 m s20 1,000 m f 10 m w C6% 175 m s18 2,000 m f5 m w C5% 200 m s21 4,000 m f 2.5 m w C4% 250 m s22 8.1 7.4 ?00 800 ?00 v o ?v 0 100 200 300 400 500 600 700 8 7.9 7.8 7.7 7.6 7.5 time ?? figure 20. p redicted response for 24 a step load change in load current, di/dt = 12 a/ m s, for c load = 500 m f and r esr = 20 m w obsolete
addc02808pb rev. 0 C9C 8.1 7.4 ?00 800 ?00 v o ?v 0 100 200 300 400 500 600 700 8 7.9 7.8 7.7 7.6 7.5 time ?? figure 21. p redicted response for 24 a step load change in load current, di/dt = 12 a/ m s, for c load = 2,000 m f and r esr = 5 m w 8.1 7.4 ?00 800 ?00 0 100 200 300 400 500 600 700 8 7.9 7.8 7.7 7.6 7.5 v o ?v time ?? figure 22. p redicted response for 24 a step load change in load current, di/dt = 12 a/ m s, for c load = 4,000 m f and r esr = 2.5 m w factory set internal compensation if the user knows the external load capacitance and r esr to be used in the application and if the application requires better pulse response than is summarized in table i, then the internal feedback compensation can be modified at the factory to im- prove the transient response. in these instances, the compensa- tion is optimized for a particular c load at the expense of performing well over a broader range of c load . the predicted maximum output voltage deviation and settling times for fac- tory-modified feedback compensation are shown in figures 23, 24, and 25, and summarized in table ii, for three combinations of c load and r esr . as can be seen, optimizing the compensa- tion for a given load capacitance gives the best transient re- sponse in terms of both voltage deviation and settling time. table ii. output response to a 24 a (1 a-25 a) step in load current (compensation optimized) typical settling time see c load r esr deviation (within 1%) figure 1,000 m f 10 m w C4% 125 m s23 2,000 m f5 m w C2.5% 100 m s24 4,000 m f 2.5 m w C1% 0 m s25 connection to load pulse performance is dependent on minimizing the parasitic im- pedances in the connection between the converter output and the load and external capacitors. low inductance and low resis- tance connections should be used. multilayer connections should be avoided to minimize stray capacitance. the converter should be placed as close to the load and external capacitors as possible. 8.1 7.4 ?00 800 ?00 v o ?v 0 100 200 300 400 500 600 700 8 7.9 7.8 7.7 7.6 7.5 time ?? figure 23. pr edicted response for 24 a step load change, di/dt = 12 a/ m s, with factory set internal compensation optimized for c load = 1,000 m f and r esr = 10 m w 8.1 7.4 ?00 800 ?00 v o ?v 0 100 200 300 400 500 600 700 8 7.9 7.8 7.7 7.6 7.5 time ?? figure 24. predicted r esponse for 24 a step load ch ange, di/dt = 12 a/ m s, with factory set internal compensation optimized for c load = 2,000 m f and r esr = 5 m w obsolete
addc02808pb rev. 0 C10C 8.1 7.4 ?00 800 ?00 v o ?v 0 100 200 300 400 500 600 700 8 7.9 7.8 7.7 7.6 7.5 time ?? figure 25. pr edicted response for 24 a step load change, di/dt = 12 a/ m s, with factory set internal compensation optimized for c load = 4,000 m f and r esr = 2.5 m w response at end of pulse the previous section describes how the addc02808pb converter responds to the positive step change in load current that occurs at the beginning of a power pulse. this section will discuss the converters response at the end of the power pulse when the load current is abruptly returned to a small value. figures 26-29 show the converters measured output voltage as the load current is stepped from 25 a down to 4 a, 2 a, 1 a, and 0.1 a, respectively. the load capacitance is 1,000 m f with 100mv 10 0% 100 90 100? v o figure 26. output voltage transient response to a 25 a to 4 a step change in load, di/dt/ = 12 a/ m s, with 1,000 m f load capacitance (r esr = 10 m w ) 100mv 10 0% 100 90 100? v o figure 27. output voltage transient response to a 25 a to 2 a step change in load, di/dt/ = 12 a/ m s, with 1,000 m f load capacitance (r esr = 10 m w ) r esr = 10 m w . the di/dt is 12 a/ m s. as can be seen, the peak deviations for these curves are close to each other and comparable to the negative deviation shown in figure 6 for a similarly sized positive step change in load current. 100mv 10 0% 100 90 100? v o figure 28. output voltage transient response to a 25 a to 1 a step change in load, di/dt/ = 12 a/ m s, with 1,000 m f load capacitance (r esr = 10 m w ) 100mv 10 0% 100 90 1ms v o figure 29. output voltage transient response to a 25 a to 0.1 a step change in load, di/dt/ = 12 a/ m s, with 1,000 m f load capacitance (r esr = 10 m w ) what is different about these curves is the settling time. once the converters output voltage rises above nominal, the converter cannot help to discharge the load capacitor. it can only reduce its output current to zero; it cannot draw a negative current. as such, the time it takes to bring the output voltage back down to its nominal value depends on the load current during the low load portion of the cycle. the rate at which the output voltage falls to its nominal value is the load current divided by the load capacitance (including the 150 m f capacitance that is inside the converter). the smaller the load current, the longer it takes to get the output voltage back to its nominal value. during the time that the output voltage is too high, the integrator in the converters feedback circuitry is continuing to ramp out of range. as the output voltage then falls below its nominal value, it must have an undershoot error to bring the integrator back into range. as can be seen from these figures, the lower the load current, the longer the output voltage remains too high, and the longer and the greater the output voltage undershoot is. even when the load current steps down to 0.1 a, the maximum deviation of the output voltage is only about 400 mv, or 5%. however, it is important to realize that if the next power pulse occurs before this transient is over, then the output voltage will obsolete
addc02808pb rev. 0 C11C not have the response depicted in the last section. this is because the feedback integrator will not have had time to return to its normal state, and so the converters ability to respond to a positive step change in load current will be reduced. the maximum negative going deviation in the output voltage under this circumstance will then be greater than is shown in the figures of that section. should this situation arise, one approach would be to step the load current down to an intermediate value (e.g., 4 a) at the end of the power pulse, and then let this current decay to a smaller value (e.g., 0.1 a) with a time constant in the 100 m s to 200 m s range. this should permit a rapid return to a steady state condition at the end of the power pulse without requiring a large average load c urrent during the low power portion of the cycle. pin connections pins 1 and 2 ( 6 sense) pins 1 and 2 must always be connected for proper operation, although failure to make these connections will not be cata- strophic to the converter under normal operating conditions. pin 1 must always be connected to the output return and pin 2 must always be connected to +v out . these connections can be made at any one of the output pins of the converter, or remotely at the load. a remote connection at the load can adjust for voltage drops of as much as 0.25 v dc between the converter and the load. long remote sense leads can affect converter stability, although this condition is rare. the impedance of the long power leads between the converter and the remote sense point could affect the converters unity gain crossover frequency and phase margin. consult factory if long remote sense leads are to be used. pin 3 (adjust) an adjustment pin is provided so that the user can change the nominal output voltage during the prototype stage. since very low temperature coefficient resistors are used to set the output voltage and maintain tight regulation over temperature, using standard external resistors to adjust the output voltage will loosen output regulation over temperature. furthermore, since the status trip point is not changed when the output voltage is adjusted using external resistors, the status line will no longer trip at the standard levels of the newly adjusted output voltage. if necessary, modified standard units can be ordered with the necessary changes made inside the package at the factory. the adjust function is sensitive to noise, and care should be taken in the routing of connections. to make the output voltage higher, place a resistor from adjust (pin 3) to Csense (pin 1). to make the output voltage lower, place a resistor from adjust (pin 3) to +sense (pin 2). figures 30 and 31 show resistor values for a 5% change in output voltage. with regard to the range that the output voltage can be adjusted by the user, there are two concerns. as the output voltage is raised it may become difficult to maintain regulation at full power and low input voltage. as the output voltage is lowered, it may become difficult to maintain regulation at minimum power and high input line. output voltage ?% 8 7 resistance ?m w 1 99 95 98 97 96 5 4 3 2 6 figure 30. external resistor value for reducing output voltage output voltage ?% 5 4 resistance ?m w 0 101 105 102 103 104 3 2 1 figure 31. external resistor for increasing output voltage pin 4 (status) pin 4 is active high referenced to Csense (pin 1), indicating that the output voltage is typically within 5%. the pin is both pulled up and down by internal circuitry. figures 32 and 33 show the typical source and sink capabilities of the status output. refer to the paragraphs describing pin 3 (adjust) for effect on status trip point. i oh ?ma 5 4 0 0.2 1.6 0.4 v oh ?v 0.6 0.8 1.0 1.2 1.4 3 2 1 figure 32. source capability of status output obsolete
addc02808pb rev. 0 C12C when pin 6 is disconnected from input return, the converter will restart in the soft-start mode. pin 6 must be kept low for at least 2 milli- seconds to initiate a full soft start. shorter off times will result in a partial soft start. figure 35 shows the input characteristics of pin 6. pin 7 (sync) pin 7 can be used for connecting multiple converters to a master clock. this master clock can be either an externally user- supplied clock or it can be a converter that has been modified and designated as a master unit. consult factory for availability of these devices. capacitive coupling of the clock signal will insure that if the master clock stops working the individual units will continue to operate at their own internal clock frequency, thereby eliminating a potential single point failure. capacitive coupling will also permit a wider duty cycle to be used. consult factory for more information. the sync pin has an internal pull-down so it is not necessary to sink any current when driving the pin low. for user-supplied master clocks with no external circuitry, the following specifications must be met: a. frequency: 1.00 mhz min b. duty cycle: 7% min, 14% max c. high state voltage high level: 4 v min to 7 v max d. low state voltage low level: 0 v min to 3.0 v max users should note that the sync pin is referenced to the input return of the converter. if the user-supplied master clock is generated on the output side of the converter, the signal should be isolated. users should be careful about the frequency selected for the external master clock. higher switching frequencies will reduce efficiency and may reduce the amount of output power available at minimum input line. consult factory for modified standard switching frequency to accommodate system clock characteristics. pin 8 (i share ) pin 8 allows paralleled converters to share the total load cur- rent, typically within 5% at full load. to use the current share feature, connect all current share pins to each other and con- nect the sense pins on each of the converters. the current sharing function is sensitive to the differential voltage between the input return pins of paralleled converters. the current sharing function is also sensitive to noise, and care should be taken in the routing of connections. refer to figure 45 for typical appli- cation circuits using paralleled converters. pin 9 (temp) pin 9 can be used to indicate case temperature or to raise or disable the temperature at which thermal shutdown occurs. typically, 3.90 v corresponds to +25 c, with a +13.1 mv/ c change for every 1 c rise. the sensor ic (connected from pin 9 to the input return (pin 10)) has a 13.1 k w impedance. the thermal shutdown feature has been set to shut down the converter when the case temperature is nominally 110 c to 115 c. to raise the temperature at which shutdown occurs, connect a resistor with the value shown in figure 36 from pin 9 to the input return (pin 10). to completely disable the temperature shutdown feature, connect a 50 k w resistor from pin 9 to the input return (pin 10). i ol ?ma 1.0 0.8 0.0 1.0 19.0 4.0 7.0 v ol ?v 10.0 13.0 16.0 0.6 0.4 0.2 figure 33. sink capability of status output pin 5 (v aux ) pin 5 is referenced to the input return and provides a semi- regulated 14 v to 16 v dc voltage supply for miscellaneous system use. the maximum permissible current draw is 5 ma and the voltage varies with the output load of the converter shown in figure 34. 10 v aux ?v converter output current ?a 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 16 15 14 13 12 11 figure 34. pin 6 (inhibit) pin 6 is active low and is referenced to the input return of the converter. connecting it to the input return will turn the converter off. for normal operation, the inhibit pin is internally pulled up to 12 v. use of an open collector circuit is recommended. v il ?v 1.2 1.1 0.7 0.5 2.0 i il ?ma 1.0 1.5 1.0 0.9 0.8 figure 35. input characteristics of pin 6 when pulled low obsolete
addc02808pb rev. 0 C13C shutdown case temperature ? c 1400 0 120 150 125 130 135 140 145 1200 1000 800 400 200 600 resistance ?k w figure 36. external resistor value for raising temperature shutdown point input voltage range the steady state operating input voltage range for the converter is defined as 18 v to 40 v. the abnormal operating input voltage range is defined as 16 v to 50 v. in accordance with mil-std-704d, the converter can operate up to 50 v dc input for transient conditions as long as 50 milliseconds, and it can operate down to 16 v dc input for continuous operation during emergency conditions. figure 3 (typical low line dropout vs. load) shows that the converter can work continuously down to and below 16 v dc under reduced load conditions. the addc02808pb can be modified to survive, but not work through, the upper limit input voltages defined in mil-std- 704a (aircraft) and mil-std-1275a (military vehicles). mil- std-704a defines an 80 v surge that lasts for 1 second before it falls below 50 v, while mil-std-1275a defines a 100 v surge that lasts for 200 milliseconds before it falls below 50 v. in both cases, the addc02808pb can be modified to operate to specification up to the 50 v input voltage limit and to shut down and protect itself during the time the input voltage exceeds 50 v. when the input voltage falls below 50 v as the surge ends, the converter will automatically initiate a soft start. in order to survive these h igher input voltage surges, the modified converter will no longer have input transient protection, how- ever, as described below. contact the factory for information on units surviving high input voltage surges. input voltage transient protection: the converter has a transient voltage suppressor connected across its input leads to protect the unit against high voltage pulses (both positive and negative) of short duration. with the power supply connected in the typical system setup shown in figure 15, a transient voltage pulse is created across the converter in the following manner. a 20 m f capacitor is first charged to 400 v. it is then connected directly across the converters end of the two meter power lead cable through a 2 w on-state resistance mosfet. the duration of this connection is 10 m s. the pulse is repeated every second for 30 minutes. this test is repeated with the connection of the 20 m f capacitor reversed to create a negative pulse on the supply leads. (if continuous reverse voltage protection is required, a diode can be added externally in series at the expense of lower efficiency for the power system.) the converter responds to this input transient voltage test by shutting down due to its input overvoltage protection feature. once the pulse is over, the converter initiates a soft-start, which is completed before the next pulse. no degradation of converter performance occurs. thermal characteristics junction and case temperatures: it is important for the user to know how hot the hottest semiconductor junctions within the converter get and to understand the relationship between junction, case, and ambient temperatures. the hottest semiconductors in the 100 w product line of analog devices high density power supplies are the switching mosfets and the output rectifiers. there is an area inside the main power transformers that is hotter than these semiconductors, but it is within navmat guidelines and well below the curie tempera- ture of the ferrite. (the curie temperature is the point at which the ferrite begins to lose its magnetic properties.) since navmat guidelines require that the maximum junction temperature be 110 c, the power supply manufacturer must specify the temperature rise above the case for the hottest semi- conductors so the user can determine what case temperature is required to meet navmat guidelines. the thermal charac- teristics section of the specification table states the hottest junction temperature for maximum output power at a specified case temperatu re. the unit can operate to higher case temperatures than 90 c, but 90 c is the maximum temperature that permits navmat guidelines to be met. case and ambient temperatures: it is the users responsibility to properly heat sink the power supply in order to maintain the appropriate case temperature and, in turn, the maximum junction temperature. maintaining the appropriate case temperature is a function of the ambient temperature and the mechanical heat removal system. the static relationship of these variables is established by the following formula: t c = t a + ( p d r q ca ) where t c = case temperature measured at the center of the package bottom, t a = ambient temperature of the air available for cooling, p d = the power, in watts, dissipated in the power supply, r q ca = the thermal resistance from the center of the package to free air, or case to ambient. the power dissipated in the power supply, p d , can be calculated from the efficiency, h , given in the data sheets and the actual output power, p o , in the users application by the following formula: p d = p o 1 h 1 ? ? ? ? for example, at 80 w of output power and 80% efficiency, the power dissipated in the power supply is 20 w. if under these conditions, the user wants to maintain navmat deratings (i.e., a case temperature of approximately 90 c) with an ambient temperature of 75 c, the required thermal resistance, case to ambient, can be calculated as 90 = 75 + (20 r q ca )or r q ca = 0.75 c / w this thermal resistance, case to ambient, will determine what kind of heat sink and whether convection cooling or forced air cooling is required to meet the constraints of the system. obsolete
addc02808pb rev. 0 C14C system instability considerations in a distributed power supply architecture, a power source provides power to many point-of-load (pol) converters. at low frequencies, the pol converters appear incrementally as negative resistance loads. this negative resistance could cause system instability problems. incremental negative resistance: a pol converter is designed to hold its output voltage constant no matter how its input voltage varies. given a constant load current, the power drawn from the input bus is therefore also a constant. if the input voltage increases by some factor, the input current must decrease by the same factor to keep the power level constant. in incremental terms, a positive incremental change in the input voltage results in a negative incremental change in the input current. the pol converter therefore looks, incrementally, as a negative resistor. the value of this negative resistor at a particular operating point, v in , i in , is: r n = v in i in note that this resistance is a function of the operating point. at full load and low input line, the resistance is its smallest, while at light load and high input line, it is its largest. potential system instability: the preceding analysis assumes dc voltages and currents. for ac waveforms the incremental input model for the pol converter must also include the effects of its input filter and control loop dynamics. when the pol converter is connected to a power source, modeled as a voltage source, v s, in series with an inductor, l s , and some positive resistor, r s , the network of figure 37 results. l p c p ?r n | adi dc/dc converter l s r s v s input terminals figure 37. model of power source and pol converter connection the network shown in figure 37 is second order and has the following characteristic equation: s 2 ( l s + l p ) c + s ( l s + l p ) | r n | + r s c p ? ? ? ? + 1 = 0 for the power delivery to be efficient, it is required that r s << r n . for the system to be stable, however, the following relationship must hold: c p | r n | > ( l s + l p ) r s or r s > ( l s + l p ) c p | r n | notice from this result that if (l s + l p ) is too large, or if r s is too small, the system might be unstable. this condition would first be observed at low input line and full load since the absolute value of r n is smallest at this operating condition. if an instability results and it cannot be corrected by changing l s or r s , such as during the mil-std-461d tests due to the lisn requirement, one possible solution is to place a capacitor across the input of the pol converter. another possibility is to place a small resistor in series with this extra capacitor. the analysis so far has assumed the source of power was a voltage source (e.g., a battery) with some source impedance. in some cases, this source may be the output of a front-end (fe) converter. although each fe converter is different, a model for a typical one would have an lc output filter driven by a voltage source whose value was determined by the feedback loop. the lc filter usually has a high q, so the compensation of the feedback loop is chosen to help dampen any oscillations that result from load transients. in effect, the feedback loop adds positive resistance to the lc network. when the pol converter is connected to the output of this fe converter, the pols negative resistance counteracts the effects of the fes positive resistance offered by the feedback loop. depending on the specific details, this might simply mean that the fe converters transient response is slightly more oscillatory, or it may cause the entire system to be unstable. for the addc02808pb, l p is approximately 0.5 m h and c p is approximately 4 m f. figure 8 shows a more accurate depiction of the input impedance of the converter as a function of frequency. the negative resistance is, itself, a very good incremental model for the power state of the converter for frequencies into the several khz range (see figure 8). navmat derating navmat is a navy power supply reliability manual that is frequently cited by specifiers of power supplies. a key section of navmat p4855-1a discusses guidelines for derating designs and their components. the two key derating crit eria are voltage derating and power derating. voltage derating is done to reduce the possibility of electrical breakdown, whereas power derating is done to maintain the component material below a specified maximum temperature. while power deratings are typically stated in terms of current limits (e.g., derate to x% of maximum rating), navmat also specifies a maximum junction tem- perature of the semiconductor devices in a power supply. the navmat component deratings applicable to the addc02808pb are as follows: resistors 80% voltage derating 50% power derating capacitors 50% voltage and ripple voltage derating 70% ripple current derating transformers and inductors 60% continuous voltage and current derating 90% surge voltage and current derating 20 c less than rated core temperature 30 c below insulation rating for hot spot temperature 25% insulation breakdown voltage derating 40 c maximum temperature rise transistors 50% power derating 60% forward current (continuous) derating 75% voltage and transient peak voltage derating 110 c maximum junction temperature obsolete
addc02808pb rev. 0 C15C diodes (switching, general purpose, rectifiers) 70% current (surge and continuous) derating 65% peak inverse voltage derating 110 c maximum junction temperature diodes (zeners) 70% surge current derating 60% continuous current derating 50% power derating 110 c maximum junction temperature microcircuits (linears) 70% continuous current derating 75% signal voltage derating 110 c maximum junction temperature the addc02808pb can meet all the derating criteria listed above. however, there are a few areas of the navmat deratings where meeting the guidelines unduly sacrifices performance of the circuit. therefore, the standard unit makes the following exceptions. common-mode emi filter capacitors: the standard supply uses 500 v capacitors to filter common-mode emi. navmat guidelines would require 1000 v capacitors to meet the 50% voltage derating (500 v dc input to output isolation), resulting in less common-mode capacitance for the same space. in typical electrical power supply systems, where the load ground is eventually connected to the source ground, common- mode voltages never get near the 500 v dc rating of the standard supply. t herefore, a lower voltage rating capacitor (500 v) was chosen to fit more capacitance in the same space in order to better meet the conducted emissions requirement of mil- std-461d (ce102). for those applications which require 250 v or less of isolation from input to output, the present designs would meet navmat guidelines. switching transistors: 100 v mosfets are used in the standard unit to switch the primary side of the transformers. their nominal off-state voltage meets the navmat derating guidelines. when the mosfets are turned off, however, momentary spikes occur that reach 100 v. the present generation of mosfets are rated for repetitive avalanche, a condition that was not considered by the navmat deratings. in the worst case condition, the energy dissipated during avalanche is 1% of the devices rated repetitive avalanche energy. to meet the navmat derating, 200 v mosfets could be used. the 100 v mosfets are used instead for their lower on-state resistance, resulting in higher efficiency for the power supply. navmat junction temperatures: the two types of power deratings (current and temperature) can be independent of one another. for instance, a switching diode can meet its derating of 70% of its maximum current, but its junction temperature can be higher than 110 c if the case temperature of the converter, which is not controlled by the manufacturer, is allowed to go higher. since some users may choose to operate the power supply at a case temperature higher than 90 c, it then becomes important to know the temperature rise of the hottest semiconductors. this is covered in the specification table in the section entitled thermal characteristics. emi considerations figures 11 through 14 show the results of emi measurements conducted in accordance with mil-std-461d/462d for the addc02805sa dc/dc converter (28 v in , 5 v out , 100 w) using the test setup shown in figure 15. the emi performance of the addc02808pb dc/dc converter will be different for several reasons. the purpose of this section is to describe the various mil-std-461d baseline tests and the addc02805sa converters corresponding performance and then explain how the emi performance of the addc02808pb will differ from this baseline. 28 v in , 100 w out, baseline performance: the addc02805sa has an integral differential- and common- mode emi filter that is designed to meet all applicable requirements in mil-std-461d when the power converter is installed in a typical system setup (described below). the converter also contains transient protection circuitry that permits the unit to survive short, high voltage transients across its input power leads. electromagnetic interference (emi) is governed by mil-std- 461d, which establishes design requirements, and mil-std- 462d, which defines test methods. emi requirements are categorized as follows (xxx designates a three digit number): cexxx: conducted emissions (emi produced internal to the power supply which is conducted externally through its input power leads) csxxx: conducted susceptibility (emi produced external to the power supply which is conducted internally through the input power leads and may interfere with the supplys operation) rexxx: radiated emissions (emi produced internal to the power supply which is radiated into the surrounding space) rsxxx: radiated susceptibility (emi produced external to the power supply which radiates into or through the power supply and may interfere with its proper operation) it should be noted that there are several areas of ambiguity with respect to ce102 measurements that may concern the systems engineer. one area of ambiguity in this measurement is the nature of the load. if it is constant, then the ripple voltage on the converters input leads is due only to the operation of the converter. if, on the other hand, the load is changing over time, this variation causes an additional input current and voltage ripple to be drawn at the same frequency. if the frequency is high enough, the converters filter will help attenuate this se cond source of ripple, but if it is below approximately 100 khz, it will not. the system may then not meet the ce102 requirement, even though the converter is not the source of the emi. if this is the case, additional capacitance may be needed across the load or across the input to the converter. another ambiguity in the ce102 measurement concerns common- mode voltage. if the load is left unconnected from the ground plane (even though the case is grounded), the common- mode ripple voltages will be smaller than if the load is grounded. the test specifications do not state which procedure should be used. however, in neither case (load grounded or floating) will the typical emi test setup described below be exactly representative of the final system configuration emi test. for the following reasons, the same is true if separately packaged emi filters are used. obsolete
addc02808pb rev. 0 C16C in almost all systems the output ground of the converter is ultimately connected to the input ground of the system. the parasitic capacitances and inductances in this connection will affect the common-mode voltage and the ce102 measurement. in addition, the inductive impedance of this ground connection can cause resonances, thereby affecting the performance of the common-mode filter in the power supply. in response to these ambiguities, the analog devices converter has been tested for ce102 under a constant load and with the output ground floating. while these measurements are a good indication of how the converter will operate in the final system configuration, the user should confirm ce102 testing in the final system configuration. ce101: this test measures emissions on the input leads in the frequency range between 30 hz and 10 khz. the intent of this requirement is to ensure that the dc/dc converter does not corrupt the power quality (allowable voltage distortion) on the power busses present on the platform. there are several ce101 limit curves in mil-std-461d. the most stringent one app-licable for the converter is the one for submarine applications. figure 11 shows that the converter easily meets this requirement (the return line measurement is similar). the components at 60 hz and its harmonics are a result of ripple in the output of the power source used to supply the converter. ce102: this test measures emissions in the frequency range between 10 khz and 10 mhz. the measurements are made on both of the input leads of the converter which are connected to the power source through lisns. the intent of this requirement in the lower frequency portion of the requirement is to ensure that the dc/dc converter does not corrupt the power quality (allowable voltage distortion) on the power busses present on the platform. at higher frequencies, the intent is to serve as a separate control from re102 on potential radiation from power leads which may couple into sensitive electronic equipment. figure 12 shows the ce102 limit and the measurement taken from the +v in line. while the measurement taken from the input return line is slightly different, both comfortably meet the mil-std-461d, ce102 limit. cs101: this test measures the ability of the converter to reject low frequency differential signals, 30 hz to 50 khz, injected on the dc inputs. the measurement is taken on the output power leads. the intent is to ensure that equipment performance is not degraded from ripple voltages associated with allowable distortion of power source voltage waveforms. figure 7 shows a typical audio susceptibility graph. note that according to the mil-std-461d test requirements, the injected signal between 30 hz and 5 khz has an amplitude of 2 v rms and from 5 khz to 50 khz the amplitude decreases inversely with frequency to 0.2 v rms. the curve of the injected signal should be multiplied by the audio susceptibility curve to determine the output ripple at any frequency. when this is done, the worst case output ripple at the frequency of the input ripple occurs at 5 khz, at which point there is typically a 25 mv peak-to-peak output ripple. it should be noted that mil-std-704 has a more relaxed requirement for rejection of low frequency differential signals injected on the dc inputs than mil-std-461d. mil-std- 704 calls for a lower amplitude ripple to be injected on the input in a narrower frequency band, 10 hz to 20 khz. cs114: this test measures the ability of the converter to operate correctly during and after being subjected to currents injected into bulk cables in the 10 khz to 400 mhz range. its purpose is to simulate currents that would be developed in these cables due to electromagnetic fields generated by antenna transmissions. the converter is designed to meet the requirements of this test when the current is injected on the input power leads cable. consult factory for more information. cs115: this test measures the ability of the converter to operate correctly during and after being subjected to 30 ns long pulses of current injected into bulk cables. its purpose is to simulate transients caused by lightning or electromagnetic pulses. the converter is designed to meet this requirement when applied to its input power leads cable. consult factory for more information. cs116: this test measures the ability of the converter to operate correctly during and after being subjected to damped sinusoid transients in the 10 khz to 100 mhz range. its purpose is to simulate current and voltage waveforms that would occur when natural resonances in the system are excited. the converter is designed to meet this requirement when applied to its in put power leads cable. consult factory for more information. re101: this requirement limits the strength of the magnetic field created by the converter in order to avoid interference with sensitive equipment located nearby. the measurement is made from 30 hz to 100 khz. the most stringent requirement is for the navy. figure 13 shows the test results when the pickup coil is held 7 cm above the converter. as can be seen, the converter easily meets this requirement. re102: this requirements limits the strength of the electric field emissions from the power converter to protect sensitive receivers from interference. the measurement is made from 10 khz to 18 ghz with the antenna oriented in the vertical plane. for the 30 mhz and above range the standard calls for the measurement to be made with the antenna oriented in the horizontal plane, as well. in a typical power converter system setup, the radiated emis- sions can come from two sources: 1) the input power leads as they extend over the two meter distance between the lisns and the converter, as required for this test, and 2) the converter output leads and load. the latter is likely to create significant emissions if left uncovered since minimal emi filtering is provided at the converters output. it is typical, however, that the power supply and its load would be contained in a conductive enclosure in applications where this test is applicable. a metal screen enclosure was therefore used to cover the converter and its load for this test. figure 14 shows test results for the vertical measurement and compares them against the most stringent re102 requirement; the horizontal measurement (30 mhz and above) was similar. as can be seen, the emissions just meet the standard in the 18 mhzC28 mhz range. this component of the emissions is due to common-mode currents flowing through the input power leads. as mentioned in the section on ce102 above, the level of common-mode current that flows is dependent on how the load is connected. this measurement is therefore a good indication of how well the converter will perform in the final configuration, but the user should confirm re102 testing in the final system. obsolete
addc02808pb rev. 0 C17C rs101: this requirement is specialized and is intended to check for sensitivity to low frequency magnetic fields in the 30 hz to 50 khz range. the converter is designed to meet this require- ment. consult factory for more information. rs103: this test calls for correct operation during and after the unit under test is subjected to radiated electric fields in the 10 khz to 40 ghz range. the intent is to simulate electromagnetic fields generated by antenna transmissions. the converter is designed to meet this requirement. consult factory for more information. circuit setup for emi test figure 15 shows a schematic of the test setup used for the emi measurements discussed above. the output of the converter is connected to a resistive load designed to draw full power. there is a 0.1 m f capacitor placed acr oss this resistor that typifies by- pass capacitance normally used in this application. at the input of the converter there are two differential capacitors (the larger one having a series resistance) and two small common-mode capacitors connected to case ground. the case itself was con- nected to the metal ground plane in the test chamber. for the re102 test, a metal screen box was used to cover both the converter and its load (but not the two meters of input power lead cables). this box was also electrically connected to the metal ground plane. with regard to the components added to the input power lines, the 100 m f capacitor with its 1 w series resistance is required to achieve system stability when the unit is powered through the lisns, as the mil-std-461d standard requires. these lisns have a series inductance of 50 m h at low frequencies, giving a total differential inductance of 100 m h. as explained earlier in the system instability section, such a large series source inductance will cause an instability as it interacts with the converters negative incremental input resistance unless some corrective action is taken. the 100 m f capacitor and 1 w resistor provide the stabilization required. it should be noted that the values of these stabilization components are appropriate for a single converter load. if the system makes use of several converters, the values of the components will need to be changed slightly, but not such that they are repeated for every converter. it should also be noted that most system applications will not have a source inductance as large as the 100 m h built into the lisns. for those systems, a much smaller input capacitor could be used. the 2 m f differential-mode capacitor and the two 82 nf common-mode capacitors were added to achieve the results shown in the emi measurement figures described above. addc02808pb emi performance the emi performance of the addc02808pb power converter will be different from the addc02805sa baseline previously discussed for several reasons: 1. its maximum power is 200 w, or twice that of the addc02805sa converter. 2. its differential input filter inductors are smaller in value by a factor of two compared to those in the addc02805sa converter to accommodate input stability at the higher power level. 3. a repetitively pulsed load will cause large input currents at the fundamental frequency (and harmonics) of the pulse waveform. the result of items 1 and 2 is that the addc02808pb converter will have higher conducted and radiated emissions in the 1/2 mhz to 10 mhz range. the emissions in this range are dominated by differential currents. these currents are proportional to power, so we would expect a factor of two increase in emissions due to the 200 w operating level. it does not matter that the average power of this pulsed unit is 100 w or lower. mil-std-462d calls for measurements to be made with peak detectors that will determine the emissions during the 200 w pulse, and not average them in any way with the lower power part of the cycle. in addition, the differential emi filter in the addc02808pb converter is less effective at attenuating the ripple currents than is the filter in the addc02805sa converter due to smaller value inductors. figure 38 shows the transfer functions of these two filters in the frequency range of interest. combining the factor of two and the reduced filter attenuation, figure 39 shows the ratio, in db, by which the emissions of figures 12 and 14 should be increased to estimate the emissions of the addc02808pb converter in this frequency range. from this curve the 1/2 mhz component should increase by 25 db, and the 1 mhz and higher components should increase by 22 db. for both conducted and radiated tests, this increase would require some additional differential filtering to meet the most stringent mil-std-461d levels shown in the figures. this could be done, for example, by increasing the 2 m f ceramic (low parasitic inductance) capacitor placed across the input of the converter in figure 15 to 30 m f or, a small 0.5 m h, 16 a inductor could be placed in series between the top of the 2 m f capacitor and the +v in pin. figures 40 and 41 show the ratios, g(s) ?transfer function (dimensionless) frequency ?hz 1 10 4 1 10 7 1 10 5 1 10 6 100 10 1 0.1 0.01 0.001 10 ? 10 ? 10 ? 10 ? 10 ? addc02808pb addc02805sa figure 38. comparison of transfer functions for the input emi filters in addc02805sa and addc02808pb obsolete
addc02808pb rev. 0 C18C frequency ?hz 30 db 20 ?0 1 10 5 10 0 ?0 1 10 6 1 10 7 figure 39. change in addc02808pb differential emis- sions vs. addc02805sa emissions with the same test setup in db, by which the differential emissions would change if either of these approaches were followed. notice that the inductor solution provides substantial attenuation in the 1 mhz and higher frequency range, while the larger capacitor solution has a more uniform effect. these proposed solutions are suggestions; they have not been tested. frequency ?hz 30 db 20 ?0 1 10 5 10 0 ?0 1 10 6 1 10 7 figure 40. ch ange in addc02808pb differential emis sions vs. the addc02805sa emissions with external 30 m f capacitor frequency ?hz 30 db 20 ?0 1 10 5 10 0 ?0 1 10 6 1 10 7 figure 41. change in addc02808pb differential emi ssions vs. the addc02805sa emissions with external 0.5 m h, 16 a inductor the peak in the radiated emissions in the 20 mhzC30 mhz range of figure 14 is dominated by common-mode noise. this common-mode noise emission is changed only slightly between the addc02808pb and the addc02805sa converters since it does not depend on the power level or the differential input filter. the turns ratio on the transformer has been changed, so we expect the common-mode emissions might be 2C4 times larger. this increase could be countered by increasing the 82 nf common-mode capacitors of figure 15 correspondingly. again, this solution is a suggestion; it has not been tested. finally, the pulsed nature of the load means there will be a substantial ripple in the input current at the fundamental pulse rate and its harmonics. this ripple can be calculated once the power is known as a function of time by dividing by the input voltage. for instance, if the load switches between zero and 200 w (260 w at the input) at 1 khz with a duty ratio of 50%, the current drawn by the converter will have a 9.3 a on, 0 a off, 50% duty ratio input current waveform (260 w/28 v = 9.3 a). this waveform has an average of 4.65 a and a square wave of plus and minus 4.65 a around this average. this square wave of current has a fundamental component as well as odd harmonics (3rd, 5th, 7th, . . .). the peak of the fundamental component is (4/ p ) 4.65. the rms value of this component is .707 times the peak, or 4.2 a. with the test setup in figure 15, given the impedances of the lisns and the 100 m f capacitor with its 1 w series resistance, a 3.6 v rms waveform would result from this fundamental component of the input current. the mil-std-461d limit shown in figure 11 calls for approximately 100 mv at the 1 khz frequency. if this limit is to be met, substantial filtering at the lower frequencies will have to be added to the system. reliability considerations mtbf (mean time between failure) is a commonly used reliability concept that applies to repairable items in which failed elements are replaced upon failure. the expression for mtbf is mtbf = t/r where t = total operating time r = number of failures in lieu of actual field data, mtbf can be predicted per mil-hdbk-217. mtbf, failure rate, and probability of failure: a proper understanding of mtbf begins with its relationship to lambda ( l ), which is the failure rate. if a constant failure rate is assumed, then mtbf = 1/ l , or l = 1/mtbf. if a power supply has an mtbf of 1,000,000 hours, this does not mean it will last 1,000,000 hours before it fails. instead, the mtbf describes the failure rate. for 1,000,000 hours mtbf, the failure rate during any hour is 1/1,000,000, or 0.0001%. thus, a power supply with an mtbf of 500,000 hours would have twice the failure rate (0.0002%) of one with 1,000,000 hours. what users should be interested in is the probability of a power supply not failing prior to some time t. given the assumption of a constant failure rate, this probability is defined as r ( t ) = e l t obsolete
addc02808pb rev. 0 C19C where r(t) is the probability of a device not failing prior to some time t. if we substitute l = 1/mtbf in the above formula, then the expression becomes r ( t ) = e t mtbf this formula is the correct way to interpret the meaning of mtbf. if we assume t = mtbf = 1,000,000 hours, then the probability that a power supply will not fail prior to 1,000,000 hours of use is e C1 , or 36.8%. this is quite different from saying the power supply will last 1,000,000 hours before it fails. the probability that the power supply will not fail prior to 50,000 hours of use is e C.05 , or 95%. for t = 10,000 hours, the probability of no failure is e C.01 , or 99%. temperature and environmental factors: although the calcu lation of mtbf per mil-hdbk-217 is a det ailed process, there are two key variables that give the manufacturer signi- ficant leeway in predicting an mtbf rating. these two variables are temperature and environmental factor. therefore, for users to properly compare mtbf numbers from two different manufacturers, the environmental factor and the temperature must be identical. contact the factory for mtbf calculations for specific environmental factors and temperatures. mechanical considerations when mounting the converter into the next higher level assembly, it is important to insure good thermal contact is made between the converter and the external heat sink. poor thermal connection can result in the converter shutting off, due to the temperature shutdown feature (pin 9), or reduced reliability for the converter due to higher than anticipated junction and case temperatures. for these reasons the mounting tab locations were selected to insure good thermal contact is made near the hot spots of the converter which are shown in the shaded areas of figure 42. figure 42. hot spots (shaded areas) of dc/dc converter the pins of the converter are typically connected to the next higher level assembly by bending them at right angles, either down or up, and cutting them shorter for insertion in printed circuit board through holes. in order to maintain the hermetic integrity of the seals around the pins, a fixture should be used for bending the pins without stressing the pin-to-sidewall seals. it is recommended that the minimum distance between the package edge and the inside of the pin be 100 mils (2.54 mm) for the 40 mil (1.02 mm) diameter pins; 120 mils (3.05 mm) from the package edge to the center of the pin as shown in figure 43. 0.100" (2.54mm) 0.120" (3.05mm) figure 43. minimum bend radius of 40 mil (1.02 mm) pins c1 +28vdc 28rtn 1 2 10 11 17 16 15 14 13 12 addc02808pb ps1 rload note: value of c1 is dependent on source impedance. refer to section on system instability considerations. figure 44. typical power connections and external parts for converter +sense ps1 +sense ps2 ?ense ps1 ?ense ps2 rload v out + v out 1 2 8 10 11 17 16 15 14 13 12 addc02808pb 1 2 8 10 11 17 16 15 14 13 12 addc02808pb ps2 ps1 i share c1 +28vdc 28rtn note: value of c1 is dependent on source impedance. refer to section on system instability considerations. figure 45. typical connections for paralleling two converters obsolete
addc02808pb rev. 0 C20C c2183C7.5C10/96 printed in u.s.a. screening levels for addc02808pb screening steps industrial (kv) ruggedized industrial (tv) mil-std-883b/smd (tv/883b) pre-cap visual 100% mil-std-883, tm2017 temp cycle n/a n/a constant acceleration n/a n/a fine leak guaranteed to meet guaranteed to meet mil-std-883, tm1014 mil-std-883, tm1014 compliant to mil-prf-38534 gross leak guaranteed to meet guaranteed to meet mil-std-883, tm1014 mil-std-883, tm1014 burn-in n/a mil-std-883, tm1015, 96 hrs at +115 c case final electrical test at +25 c, per specification at +25 c, per specification table table nominal case dimensions in inches and (mm) [all tolerances .005" ( .13 mm) unless otherwise specified] 0.150 (3.81) 0.100 (2.54) 8 plcs 0.200 (5.08) 0.150 (3.81) 0.200 (5.08) 0.390 0.010 (9.91 0.25) 0.800 0.010 (20.32 0.25) 1.145 (29.08) 2 plcs 0.150 (3.81) 4 plcs top view 0.149 (3.78) dia typ 0.300 (7.62) sq 0.010 4 plcs 0.200 (5.08) 5 plcs 0.250 (6.35) 2 plcs 1.500 0.010 (38.10 0.25) 0.040 0.003 (1.02 0.08) 0.090 0.010 (2.29 0.25) 4 plcs 2.745 0.010 (69.72 0.25) 1.800 (45.72) typ 2.100 0.010 (53.34 0.25) notes 1. the final product weight is 85 grams maximum. 2. the package base material is made of molybdenum and is nominally 40 mils (1.02 mm) thick. the runout is less than 2 mils per inch (0.02 mm per cm). 3. the high current pins (10C17) are 40 mil (1.02 mm) diameter; are 99.8% copper; and are plated with gold over nickel. 4. the signal carrying pins (1C9) are 18 mil (0.46 mm) diameter; are kovar; and are plated with gold over nickel. 5. all pins are a minimum length of 0.740 inches (18.80 mm) when the product is shipped. the pins are typically bent up or down and cut shorter for proper connection into the users system. 6. all pin-to-sidewall spacings are guaranteed for a minimum of 500 v dc breakdown at standard air pressure. 7. the case outline was originally designed using the inc h-pound units of measurement. in the event of conflict between the metric and inch-pound units, the inch-pound shall take precedence. obsolete

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